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FEATURES Single Supply Pin Configurable Input Voltage Ranges Power Dissipation: 240 mW No Missing Codes Guaranteed Differential Nonlinearity Error: 0.5 LSB Complete: On-Chip Sample-and-Hold Amplifier and Voltage Reference Signal-to-Noise and Distortion Ratio: 68 dB Spurious-Free Dynamic Range: -77 dB Out of Range Indicator Binary Output Data Digital I/Os Compatible with +5 V or +3.3 V Logic 28-Pin PLCC Package
Complete 12-Bit, 3 MSPS Monolithic A/D Converter AD1672
input combined with the power and cost savings over previously available solutions will enable new designs in communications, imaging and medical applications. The AD1672 provides both reference output and reference input pins allowing the onboard reference to serve as a system reference. An external reference can also be chosen to suit the dc accuracy and temperature drift requirements of the application. The digital output data is presented in a straight binary output format for the unipolar input ranges of 0 V to 2.5 V and 0 V to 5.0 V. For the bipolar input range of -2.5 V to +2.5 V, the digital output data is presented in an offset binary format. An out-of-range (OTR) signal indicates an overflow condition. It can be used with the most significant bit to determine low or high overflow. The AD1672 is packaged in a 28-pin PLCC package and is specified for operation from -40C to +85C.
PRODUCT HIGHLIGHT
PRODUCT DESCRIPTION
The AD1672 is a monolithic, single supply 12-bit, 3 MSPS analog-to-digital converter with an on-chip, high performance sample-and-hold amplifier (SHA) and voltage reference. The AD1672 uses a multistage pipelined architecture with output error correction logic to provide 12-bit accuracy at 3 MSPS data rates and guarantees no missing codes over the full operating temperature range. The AD1672 combines a high performance BiCMOS process and a novel architecture to achieve its high performance levels. The fast settling input SHA is equally suited for both multiplexed systems that switch negative to positive full-scale voltage levels in successive channels and sampling single-channel inputs at frequencies up to the Nyquist rate. The AD1672's wideband
The AD1672 offers a complete single-chip sampling 12-bit, 3 MSPS analog-to-digital conversion function in a 28-pin PLCC package. The AD1672 at 240 mW consumes a fraction of the power of presently available solutions and provides exceptional performance relative to other monolithic solutions. OUT OF RANGE (OTR)--The OTR output bit indicates when the input signal is beyond the AD1672's input range. Ease-of-Use--The single supply AD1672 is complete with SHA voltage reference and pin strappable input ranges. It is compatible with a wide range of amplifiers.
FUNCTIONAL BLOCK DIAGRAM
AIN1 & 2 THA REF IN REFCOM REF AMP
ADC
AD1672
THA THA
DAC
ADC
THA
DAC
ADC
DAC
ADC
NOISE REDUCTION
DAC AMP 4 4 3 CORRECTION LOGIC BANDGAP REFERENCE REFCOM LATCHES CLOCK TIMER 4
2.5V REF OUTPUT
OUTPUT DATA 12 BITS
CLOCK INPUT
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. (c) Analog Devices, Inc., 1995 One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD1672-SPECIFICATIONS
DC SPECIFICATIONS (T
Parameter RESOLUTION MAX CONVERSION RATE ACCURACY Integral Nonlinearity (INL) Differential Nonlinearity (DNL) No Missing Codes Offset Error Zero Error1 Gain Error2 POWER SUPPLY REJECTION3 VCC (5.0 V 0.25 V) VDD (5.0 V 0.25 V) VDRDD (3.0 V to 5.25 V) ANALOG INPUT Input Ranges 2.5 V Range Unipolar 5.0 V Range Unipolar 5.0 V Bipolar Input Resistance 2.5 V Input Range 5.0 V Input Ranges Input Capacitance INTERNAL VOLTAGE REFERENCE Output Voltage Output Current4 REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltages VCC VDD DRVDD Supply Current IVCC IVDD IDRVDD POWER CONSUMPTION TEMPERATURE RANGE -40
MIN
to TMAX with VCC = +5.0 V, VDD = +5.0 V, DRVDD = +5.0 V, fSAMPLE = 3 MHz unless otherwise noted)
Min 12 3 -2.5 -1.0 -0.75 -0.75 -1.50 -0.30 -0.30 -0.10 1.0 0.5 12 Bits Guaranteed 0.20 0.20 0.30 2.5 1.5 0.75 0.75 1.50 0.30 0.30 0.10 AD1672AP Typ Max Units Bits MHz LSB LSB % FSR % FSR % FSR % FSR % FSR % FSR
0.0 0.0 -2.5
2.5 5.0 2.5
Volts Volts Volts
1.5 3.0
2.0 4.0 10 2.5 8.0
2.5 5.0
k k pF Volts mA k
2.475 0.5 6.0
2.525 10.0
4.75 4.75 3.00
5.0 5.0 5.0 46 1.0 0.2 240 25
5.25 5.25 5.25 65 2.0 2.0 363 85
Volts Volts Volts mA mA mA mW C
NOTES 1 Bipolar Mode. 2 Includes internal reference error. 3 Change in full scale as a function of the dc supply voltage. 4 Current available for external loads. External load should not change during conversion. Specification subject to change without notice.
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AD1672 AC SPECIFICATIONS -2.5 V to +2.5 V configuration unless otherwise noted)
Parameter SIGNAL-TO-NOISE AND DISTORTION RATIO (S/(N+D)) fINPUT = 100 kHz fINPUT = 500 kHz fINPUT = 1.5 MHz SIGNAL-TO-NOISE RATIO (SNR) fINPUT = 100 kHz fINPUT = 500 kHz fINPUT = 1.5 MHz TOTAL HARMONIC DISTORTION (THD) fINPUT = 100 kHz fINPUT = 500 kHz fINPUT = 1.5 MHz SPURIOUS FREE DYNAMIC RANGE (SFDR) fINPUT = 100 kHz fINPUT = 500 kHz fINPUT = 1.5 MHz INTERMODULATION DISTORTION (IMD)1 FULL POWER BANDWIDTH SMALL SIGNAL BANDWIDTH (-20 dB FSR) CODE TRANSITION NOISE APERTURE DELAY APERTURE JITTER ACQUISITION TO FULL-SCALE STEP OVERVOLTAGE RECOVERY TIME
NOTES 1 fs = 490 kHz; fb = 510 kHz typical value for third order products. Specifications subject to change without notice.
(TMIN to TMAX with VCC = +5 .0 V, VDD = +5.0 V, DRVDD = +5.0 V, fSAMPLE = 3 MHz, AIN = 0.5 dB in bipolar
AD1672AP Typ 68 68 60 70 70 67 -74 -74 -60 -77 -77 -61 65 5 20 1/4 9 10 150 150
Min
Max
Units dB dB dB dB dB dB dB dB dB dB dB dB dB MHz MHz LSB rms ns ps rms ns ns
63
66
-64
-65
DIGITAL SPECIFICATION (T
Parameter
MIN
to TMAX with VCC = +5 .0 V, VDD = +5.0 V, VDRVDD = +5.0 V unless otherwise noted)
Symbol VIH VIL IIH IIL CIN VOH VOL COUT Min 3.5 -10 -10 10 2.4 0.4 5 1.0 10 10 AD1672AP Typ Max Units Volts Volts A A pF Volts Volts pF
LOGIC INPUTS High Level Input Voltage Low Level Input Voltage High Level Input Current (VIN = VDD) Low Level Input Current (VIN = 0 V) Input Capacitance LOGIC OUTPUTS High Level Output Voltage (IOH = 0.5 mA) Low Level Output Voltage (IOL = 1.6 mA) Output Capacitance
Specifications subject to change without notice.
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AD1672
S1 ANALOG INPUT S2
tC tCH tCL
S2
S3
tOD
S3
INPUT CLOCK
S1
DATA OUTPUT OTR
DATA 1
DATA 2
Figure 1. Timing Diagram
SWITCHING SPECIFICATIONS
Parameter Clock Period Clock Pulse Width High Pulse Width Low Output Delay Pipeline Delay (Latency) Symbol tC tCH tCL tOD Value 334 167 167 15 30 2.5 Units ns min ns min ns min ns min ns typ Clock Cycles
ABSOLUTE MAXIMUM RATINGS*
Parameter
With Respect to
Min -0 5 -0.5 -0.5 -0.5 -0.5 -0.5 -6.5 -0.5 -65
Max +6.5 +6.5 +6.5 +0.5 VDD + 0.5 DRVDD + 0.5 +6.5 VCC + 0.5 +150 +150 +300
Units Volts Volts Volts Volts Volts Volts Volts Volts C C C
VCC ACOM VDD DCOM DRVDD DRCOM ACOM DCOM, DRCOM CLOCK DCOM Digital Outputs DCOM AIN ACOM REFIN ACOM Junction Temperature Storage Temperature Lead Temperature (10 sec)
*Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may effect device reliability.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1672 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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PIN DESCRIPTION ORDERING GUIDE
Symbol DRCOM BIT 12 BIT 2-11 BIT 1 DRVDD OTR
Pin No. 1 2 3-12 13 14 15
Model Type P DO DO DO P DO Name and Function Digital Output Driver Ground. Data Bit (LSB). Data Bits. +5 V Digital Output Driver Supply. Out of Range is Active High on the leading edge of Code 0 or the trailing edge of Code 4096. See Output Data Format Table V. Sample Clock. +5 V Digital Supply. Digital Ground. Analog Ground. 2.5 V Reference Output (Decouple with 1 F ceramic capacitor to REFCOM). Analog Input. Analog Input. Reference Input. Noise Compensation (Decouple with 1 F ceramic capacitor to ACOM). Noise Compensation (Decouple with 1 F ceramic capacitor to ACOM). Analog Ground. +5 V Analog Supply.
BIT 9 5 BIT 8 6 BIT 7 7 BIT 6 8 BIT 5 9 BIT 4 10 BIT 3 11
Temperature Range -40C to +85C
PIN CONFIGURATION
BIT 12 (LSB) NCOMP1
Package P-28A
AD1672AP
DRCOM
Data Bit (MSB).
BIT 10 BIT 11
4
3
2
1
28 27 26
PIN 1 IDENTIFIER
VCC
ACOM
25 NCOMP2 24 REFCOM
AD1672
TOP VIEW (Not to Scale)
23 REFIN 22 AIN2 21 AIN1 20 REFOUT 19 REFCOM
CLOCK VDD DCOM REFCOM REFOUT
16 17 18 20
DI P P AO
19, 24 P
12 13 14 15 16 17 18 BIT 2 (MSB) BIT 1 DRVDD CLOCK OTR VDD DCOM
AIN1 AIN2 REFIN NCOMP2
21 22 23 25
AI AI AI AO
NCOMP1
26
AO
ACOM VCC
27 28
P P
TYPE: AI = Analog Input; DI = Digital Input; P = Power; AO = Analog Output; DO = Digital Output.
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AD1672
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY ERROR (INL) APERTURE DELAY
Integral nonlinearity error refers to the deviation of each individual code from a line drawn from "negative full scale" through "positive full scale." The point used as "negative full scale" occurs 1/2 LSB before the first code transition (all zeros to only the LSB on). "Positive full scale" is defined as a level 1 1/2 LSB beyond the last code transition (to all ones). The deviation is measured from the middle of each particular code to the true straight line.
DIFFERENTIAL LINEARITY ERROR (DNL, NO MISSING CODES)
Aperture delay is a measure of the Sample-and-Hold (SHA) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion.
OVERVOLTAGE RECOVERY TIME
Overvoltage recovery time is defined as that amount of time required for the ADC to achieve a specified accuracy after an overvoltage (50% greater than full-scale range), measured from the time the overvoltage signal reenters the converter's range.
DYNAMIC SPECIFICATIONS
SIGNAL-TO-NOISE AND DISTORTION (S/N+D) RATIO
An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. Guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes must be present over all operating ranges.
UNIPOLAR OFFSET ERROR
S/N+D is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the Nyquist frequency, including harmonics but excluding dc. The value for S/N+D is expressed in decibels.
TOTAL HARMONIC DISTORTION (THD)
In the unipolar mode, the first transition should occur at a level 1/2 LSB above analog common. Unipolar offset is defines as the deviation of the actual from that point.
BIPOLAR ZERO ERROR
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal and is expressed as a percentage or in decibels.
INTERMODULATION DISTORTION (IMD)
In the bipolar mode, the major carry transition should occur for an analog value 1/2 LSB below analog common. Zero error is defined as the deviation of the actual transition from that point.
GAIN ERROR
The first transition should occur for an analog value 1/2 LSB above nominal negative full scale. The last transition should occur for an analog value 1 1/2 LSB below the nominal full scale. Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions.
POWER SUPPLY REJECTION
With inputs consisting of sine waves at two frequencies, fa and fb, any device with nonlinearities will create distortion products, of order (m + n), at sum and difference frequencies of mfa nfb, where m, n = 0, 1, 2, 3. . . . Intermodulation terms are those for which m or n is not equal to zero. For example, the second order terms are (fa + fb) and (fa - fb) and the third order terms are (2 fa + fb), (2 fa - fb), (fa + 2fb) and (2 fb - fa). The IMD products are expressed as the decibel ratio of the rms sum of the measured input signals to the rms sum of the distortion terms. The two signals are of equal amplitude and the peak value of their sums is -0.5 dB from full-scale. The IMD products are normalized to a 0 dB input signal.
FULL-POWER BANDWIDTH
One of the effects of power supply error on the performance of the device will be a small change in gain. The specifications show the maximum change in the converter's full scale as the supplies are varied from minimum to maximum values.
APERTURE JITTER
The full-power bandwidth is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3 dB for a full-scale input.
SPURIOUS FREE DYNAMIC RANGE
Aperture jitter is the variation in aperture delay for successive samples and is manifested as noise on the input to the A/D.
CODE TRANSITION NOISE
The difference, in dB, between the rms amplitude of the input signal and the peak spurious signal.
The effects of noise are to introduce an uncertainty in the precise determination of the analog input values at which the output code transitions take place, and, in effect, to increase or reduce the quantization band. Code transition noise describes the quantization band variation resulting from noise in terms of rms LSBs.
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Typical Performance Characteristics-AD1672 AD1672
Sample Rate: 3 MSPS and AIN = -0.5 dB
1.0 0.8 0.6
DNL ERROR - LSB
INL ERROR - LSB
2.5 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0
0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 500 1000 1500 2000 CODE 2500 3000 3500 4000
-2.5
0
500
1000
1500
2000 CODE
2500
3000
3500
4000
Figure 2. Typical DNL Performance
Figure 4. Typical INL Performance
80 75
70
68
70
S/(N+D) - dB
-0.5dB
66
500kHz 1MHz
65 60 55
- 6.0dB
S/(N+D) - dB
64 1.5MHz 62
- 20.0dB 50
60
45 40 105
58 -10
106 INPUT FREQUENCY - Hz
107
-9
-8
-7
-6 -4 -5 AMPLITUDE - dB
-3
-2
-1
0
Figure 3. S/(N+D) vs. Input Frequency
Figure 5. S/(N+D) vs. Amplitude
-40
-50
AMPLITUDE - dB
-60
-70 THD 2nd HARM -80 3rd HARM -90 105
106 INPUT FREQUENCY - Hz
107
Figure 6. Distortion vs. Input Frequency, Full-Scale Input
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AD1672-Dynamic Characteristics
Sample Rate: 3 MSPS and AIN = -0.5 dB
1 THD = -74.42dB S/(N+D) = 68.83dB SFDR = -78.79dB HARMONICS - dB 2ND -79 6TH 3RD -86 7TH 4TH -78 8TH 5TH -81 9TH THD = -60.12dB S/(N+D) = 59.70dB SFDR = - 61.09dB HARMONICS - dB 2ND -61 3RD -67 4TH -98 5TH -78 6TH 7TH 8TH 9TH -79 -91 -93 -87 3 2 6 9 4 8 7 5 1
-86 -93 -95 -96
5 6 7
4
2 3 89
15dB/DIV
15 dB/DIV
Figure 7. Typical FFT, fIN = 525 kHz
Figure 8. Typical FFT, fIN = 1.450 MHz
THEORY OF OPERATION
The AD1672 is implemented using a 4-stage pipelined multiple flash architecture. The flash resolution for the stages is 4-4-3-4 with one-bit of overlap used between stages for error correction. A low noise sample-and-hold amplifier (SHA) acquires a fullscale, single-ended input to 12-bit accuracy within 167 ns. A 4-bit approximation of the input is made by the first flash converter, and an accurate analog representation of this four-bit estimate is generated by a digital-to-analog (DAC) converter. This approximation is subtracted from the SHA output to produce a remainder, or residue. This residue is then sampled and held by the second SHA, and a 4-bit approximation is generated and subtracted by the second stage. Once the second SHA goes into hold, the first stage goes back into sample mode to acquire a new input signal. The third stage which has 3 bits of resolution is similar to the first and second stage in that each stage consists of a SHA, flash ADC, and a DAC. Each stage preforms a 4- (or 3-) bit approximation/subtraction operation with the residue of each stage being passed on to the next stage. The fourth or last stage consists only of a 4-bit flash ADC which converts the final residue. The 15 output bits from the 4 flash converters are accumulated in the correction logic block, which adds the bits together using the appropriate correction algorithm, to produce the 12 bit output word. The digital output, together with the overrange indicator (OTR), is latched into an output buffer to drive the output pins. The additional SHA inserted in each stage of the AD1672 architecture allows pipelining of the conversion. In essence, the converter is converting multiple inputs simultaneously, processing them through the converter chain serially. This means that
while the converter is capable of capturing a new input sample every clock cycle, it actually takes 2 1/2 clock cycles for the conversion to be fully processed and appear at the output. This "pipeline delay" is often referred to as latency, and is not a concern in most applications, however there are some cases where it may be a consideration. For example, some applications call for the A/D converter to be placed in a high speed feedback loop, where its input is servoed to provide a desired result at the digital output (e.g., offset calibration or zero restoration in video applications). In these cases the clock cycle delay through the pipeline must be accounted for in the loop stability calculations. Also, because the converter is working on three conversions simultaneously major disruptions to the part (such as a large glitch on the supplies or reference) may corrupt three data samples. Finally, there will be a minimum clock rate below which the SHA droop corrupts the signal in the pipeline. In the case of the AD1672, this minimum clock rate is 20 kHz at 25C. The AD1672 clock circuitry uses both edges of the clock in its internal timing circuitry (see specification page for exact timing requirements). The AD1672 samples the analog input on the rising edge of the clock input. During the clock low time (between the falling edge and rising edge of the clock), the input SHA is in sample mode; during the clock high time it is in hold. System disturbances just prior to the rising edge of the clock may cause the part to acquire the wrong value, and should be minimized. While the part uses both clock edges for its timing, jitter is only a significant issue for the rising edge of the clock (see CLOCK INPUT section).
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AD1672
APPLYING THE AD1672
ANALOG INPUTS
C1 10F ANALOG INPUT 21 AIN1 C2 1.0F ANALOG INPUT C1 10F 21 AIN1 C2 1.0F
Figure 9 shows the equivalent analog input of the AD1672. The input SHA and associated resistor network topology can be easily configured for either unipolar (0 V to 2.5 V, 0 V to 5.0 V) or bipolar (-2.5 V to 2.5 V) input signals as shown in Figure 10. The nominal input resistance, RIN, of the AD1672 is 2 k for a 2.5 V span and 4 k for a 5 V span. The circuit topology both level shifts and inverts the analog input for the various input spans.
VBIAS 1.25V 4k AIN 1 4k AIN 2 2k 2k SHAOUT
AD1672
22 AIN2
AD1672
22 AIN2
10F 25 NCOMP2 1.0F 20
10F 25 NCOMP2 1.0F 20
REF OUT
REF OUT
23 REFIN
23 REFIN
2.5V Span
5.0V Span
Figure 11. AC Coupled Inputs
Figure 9. Equivalent Analog Input Circuit
VIN 21 AIN1 22 AIN2 VIN 21 AIN1 22 AIN2
AD1672
20 REFOUT 23 REFIN 1F 1F
AD1672
20 REFOUT 23 REFIN
In applications requiring dc coupling, a buffer amplifier is recommended for driving the AD1672 input. Any source resistance will contribute to both gain and offset error due to its interaction with the AD1672's input resistance. The particular application and signal input range will determine how the buffer amplifier is configured. For example, in dc precision applications, the buffer amplifier can be configured for convenient gain and offset adjustment as shown in Figure 12. In spectral analysis/signal processing applications, the buffer amplifier can be configured as a 2nd order antialiasing filter in a Sallen-Key or Multiple-Feedback topology as shown in Figure 13.
GAIN ADJUSTMENT 500 50 500
a. 0 to +2.5 V Input Range
VIN
b. 0 to +5.0 V Input Range
ANALOG INPUT
VCC
21 AIN1 22 AIN2
AD1672
5k OFFSET 50 ADJUSTMENTS 5k VEE 0.1F AIN
AD1672
20 REFOUT 23 REFIN 1F
c. -2.5 to +2.5 V Input Range
Figure 12. Offset and Gain Adjustment
R3 C2 VIN R1 R2 VOUT C1 R4 C1 R3 VIN R1 R2 C2
Figure 10. Input Range Connections
In applications where ac coupling of the analog input signal is appropriate such as in a single supply system, the user can capacitively couple the input signal for a 2.5 V or 5 V span thus removing any preceding system dc offsets. Figure 11 shows the proper configurations of the AD1672 for ac coupling. Maintaining the specifications outlined in the data sheet requires careful selection of the component values. The most important concern is that the f -3 dB high pass corner is a function of C1 and C2 in parallel with RIN. The f -3 dB point can be approximated by the equation
VOUT
Figure 13. Sallen-Key and Multiple-Feedback Antialiasing Filter Topologies
f -3 dB = 1 / (2 x x RIN x CEQ ) /
where CEQ is the parallel combination of C1 and C2. Note that C1 is typically a large electrolytic or tantalum capacitor that becomes inductive at high frequencies. Adding a small ceramic capacitor on the order of 0.1 F that does not become inductive until negligibly higher frequencies maintains a low impedance over a wide frequency range.
In imaging and multiplexed data acquisition applications, the AD1672's wide input bandwidth facilitates rapid acquisition of transient input signals: the input SHA can typically settle to 12bit accuracy from a full scale input step in less than 150 ns. Figure 14 illustrates the typical acquisition of a full scale input step. For amplifiers that are powered by supplies greater than 6.5 V, it is recommended that a clamping circuit be included at the input of AD1672. This circuit limits the input voltage to 6.5 V under a fault condition.
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AD1672
4500 4000 3500
CODE OUT
3000 2500 2000 1500 1000 500 0 0 20 40 60 80 nsec 100 120 140 160
The selection of the buffer is of particular concern in preserving the performance of the AD1672. The total output referrednoise contribution of the selected amplifier should be less than 200 V rms to preserve the AD1672's noise performance. The amplifiers harmonic distortion should be 12 dB or better in performance than the AD1672 over the bandwidth and signal level range of the particular application. The selected amplifier should settle to 0.01% within 70 ns. Table I lists the performance of various suitable amplifiers when configured for a gain of +1 or -1 with the AD1672 configured for 2.5 V bipolar operation and fCLOCK = 3 MHz. The AD80xx family of high speed amplifiers are only suitable for 2.5 V bipolar and 0 V-2.5 V unipolar operation due to their powersupply range and voltage output swing constraints. Note that the SNR, THD, and SFDR results in Tables I, II and III are for a 750 kHz full-scale (-0.5 dB) input signal. These results were determined experimentally using the AD1672 evaluation board, and hence the stated amplifier's performance is inclusive of the AD1672.
Table I. -2.5 V to +2.5 V Range
Figure 14. Typical AD1672 Settling Time
The AD1672 will contribute its own wideband thermal noise. As a result of the integrated wideband noise (1/4 LSB rms, referred-to-input), applying a dc analog input produces more than one code at the output. A histogram analysis of the AD1672 with a dc input is shown in Figure 15. It shows a bell shaped curve consistent with the Gaussian nature of the thermal noise. This histogram will be approximately 3 codes wide, depending on how well the input is centered on a given code and how many samples are taken. Figure 16 illustrates the AD1672's transition noise.
2100000 1800000 1500000
# CODE HITS
ADI Part # AD8047 AD8041 AD8011 AD817 AD818 AD811 w/o Op Amp
SNR 70.5 70.0 70.5 70.4 70.3 70.3 70.5
THD -67.5 -67.3 -67.0 -62.1 -65.0 -61.9 -67.5
SFDR -68.4 -68.2 -67.8 -62.9 -68.0 -63.4 -68.4
Gain +1 +1 +1 +1 -1 +1
2015807
1200000 900000 600000
Table II lists the performance of three high speed amplifiers which are configured for a gain of +1 or -1 with the AD1672 configured for 0 V to 5 V unipolar operation and fCLOCK = 3 MHz. Note that these amplifiers may operate at the higher power supply range to achieve the 0 V to 5 V output swing.
13639 67324
300000
Table II. 0 V to +5 V Range
0
-1 0 +1 DEVIATION FROM CORRECT CODE - LSB
Figure 15. Typical Grounded Histogram
100 90 80
100 x p ( CODE X + 1)
ADI Part # AD811 AD817 AD818
SNR 70.1 70.1 70.0
THD -67.6 -68.9 -67.4
Settling Time (ns) to 0.01% 65 70 80
Gain +1 +1 -1
70 60 50 40 30 20 10 0 CODE X CODE X / 1
= 0.25 LSB RMS
Table III lists the performance of two high speed amplifiers specified for single supply operation. They are configured for a gain of +1 with the AD1672 configured for 0 V to 2.5 V unipolar operation and fCLOCK = 3 MHz. The output of these amplifiers are ac coupled to the AD1672.
Table III. AC Coupled 0 V to 2.5 V Range
ADI Part # AD8011 AD8041
SNR 70.1 69.7
THD -70.0 -71.3
SFDR -71.6 -73.4
Figure 16. Code Probability at a Transition
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AD1672
REFERENCE INPUT REFERENCE OUTPUT
The nominal reference input is 2.5 V, taken with respect to REFCOM. The reference input pin (REFIN) can be connected to the reference output pin (REFOUT) or a standard external +2.5 Volt reference can be selected to meet specific system requirements. Figure 17 shows the AD1672's REFIN being driven from an external precision voltage reference such as the REF192. If an external reference is used, REFOUT can be effectively disabled by tying it directly to the positive supply voltage VCC. Note that if the reference is changed during a conversion, all three conversions in the pipeline will be invalidated. The nominal 2.5 V reference input is rescaled to 1.25 V via a resistor divider network as shown in Figure 18. The nominal resistance of this resistor network is 8 k. Table IV summarizes various 2.5 V references for use with the AD1672 (see REFERENCE OUTPUT section).
Table IV. Suitable 2.5 Volt References
The AD1672 includes an onboard +2.5 V curvature compensated bandgap reference that has been laser trimmed for both absolute value and temperature drift. The reference must be externally compensated with a capacitor of 1 F or greater from REFOUT to REFCOM. The reference is specified to provide an additional load current up to 500 A. For large dynamic loads and/or external loads greater than 500 A, an external buffer amplifier or pull-up resistor is required. If a pull-up resistor is used, its value should be selected such that REFOUT will not be required to sink any current under all operating conditions. Figure 19 illustrates the load regulation of the reference. The power supply rejection of the reference is better than 0.2 % of FSR at dc.
2.500 2.499 2.498
REFERENCE VOLTAGE - Volts
Drift (ppm/ C) REF43B REF192E AD780B 10 (max) 5 (max) 3 (max)
+VCC
Initial Accuracy % 0.1 0.08 0.04
2.497 2.496 2.495 2.494 2.493 2.492 2.491
AD780
+VCC 10F 0.1F GND OUTPUT 1F VS
REFOUT
2.490 0 100 200 300 400 500 600 700 LOAD CURRENT - A 800 900 1000
AD1672
REFIN
Figure 19. Reference Output Voltage vs. Load Current
DIGITAL OUTPUTS
Figure 17. Circuit using AD780 Optional +2.5 V Reference Input Circuit
Figure 18 shows the proper connection of two external 1 F capacitors, CNR1 and CNR2, associated with the two noise reduction nodes NCOMP1 and NCOMP2 (Pins 25 and 26) of the AD1672. Although these noise reduction capacitors, CNR, are not required for stability, the most optimum noise and distortion performance will be attained with a 1 F ceramic capacitor connected from each Noise Reduction node to ACOM. CNR1 is associated with the output of the DAC amp and is required for optimum distortion performance and SHA settling time. It provides a low source impedance for signal-dependent, transient currents associated with this node. CNR2 reduces the noise contribution from the reference buffer amplifier.
1F 20 REFOUT REFIN REFCOM 4k 4k
REFERENCE NOISE REDUCTION
The AD1672 output data is presented in positive true straight binary for both the 0 V to 2.5 V and 0 V to 5 V unipolar input ranges and positive true offset binary for the 2.5 V bipolar range. Table V indicates the output data formats for the three analog input ranges. Users requiring twos complement encoding for the 2.5 V range may simply invert the MSB (Pin 13).
Table V. Output Data Format
Input Voltage Range 0 to +2.5 0 to +5.0 -2.5 to +2.5
+FS (V) +2.5 +5.0 +2.5
-FS (V) 0.0 0.0 -2.5
LSB (mV) 0.610 1.22 1.22
OTR 1 0 0
DATA OUTPUTS 1111 111 1111 1111 1111 1111 1111 1111 1110 -FS+1/2 LSB OTR
+FS -1 1/2 LSB
AD1672
REF AMP
23 24 CNR2 1F 25 CNR1 1F 26
NCOMP2 DAC AMP NCOMP1
0 0 1
0000 0000 0001 0000 0000 0000 0000 0000 0000 -FS -FS -1/2 LSB +FS +FS -1/2 LSB
Figure 18. Reference Noise Reduction
Figure 20. Output Data Format
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AD1672
The AD1672's CMOS digital output drivers can be configured to interface with +5 V or +3.3 V logic families by setting DRVDD to +5 V or +3.3 V respectively . They are also sized to provide sufficient output current to drive a wide variety of logic families. However, large drive currents tend to cause glitches on the supplies and may effect S/(N+D) performance. Applications requiring the AD1672 to drive large capacitive loads or large fanout may require additional decoupling capacitors on DRVDD and DVDD. In extreme cases, external buffers or latches may be required.
OUT OF RANGE
+5V R D Q CLK 6MHz S +5V Q 3MHz
Figure 22. Divide-by-Two Clock Circuit
An out-of-range condition exists when the analog input voltage is beyond the input range (0 V to +2.5 V, 0 V to +5.0 V, 2.5 V) of the converter. OTR (Pin 15) is a digital output which is updated along with the data output pertaining to the particular sampled analog input voltage. Hence, OTR has the same pipeline delay (latency) as the digital data. It is set low when the analog input voltage is within the analog input range. It is set HIGH and will remain HIGH when the analog input voltage exceeds the input range by typically 1/2 LSB from the center of the full-scale output codes. OTR will remain HIGH until the analog input is within the input range and another conversion is completed. By logical ANDing OTR with the MSB and its complement, overrange high or underrange low conditions can be detected. Table IV is a truth table for the over/under range circuit in Figure 20 which uses NAND gates. Systems requiring programmable gain conditioning prior to the AD1672 can immediately detect an out-of-range condition, thus eliminating gain selection iterations. Also, OTR can be used for digital offset and gain calibration (see Gain and Offset Adjustment).
Table VI. Out-of-Range Truth Table
In this case, a 6 MHz clock is divided by 2 to produce the 3 MHz clock input for the AD1672. In this configuration, the duty cycle of the 6 MHz clock is irrelevant. The input circuitry for the CLOCK pin is designed to accommodate CMOS inputs. The quality of the logic input, particularly the rising edge, is critical in realizing the best possible jitter performance for the part: the faster the rising edge, the better the jitter performance. The offset of the AD1672 is sensitive to the rising edge (i.e., dV/dt) seen at CLOCK due to clock feedthrough. An additional offset component becomes noticeable for rise times below 10 ns and causes an additional few LSBs of offset. The amount of additional offset is dependent on dV/dt of the rising edge and hence will remain constant for nonvarying rising edges. For applications which are sensitive to a change in offset due to a variation in the rise edge, the CLOCK rise time may be reduced by selecting a slower logic family or installing a 1 k resistor between the clock driver and CLOCK of the AD1672. As a result, careful selection of the logic family for the clock driver, as well as the fanout and capacitive load on the clock line, is important. Jitter-induced errors become more predominant at higher frequency, large amplitude inputs, where the input slew rate is greatest. Although the AD1672 is designed to support a sampling rate of 3 MSPS, operating at slightly faster or slower clock rates may be possible with a minimum degradation in performance levels. Figure 23 is a plot of the S/(N+D) vs. clock frequency for a 500 kHz analog input. In fact, the AD1672 is capable of operating with a clock frequency as low as 20 kHz
75
OTR 0 0 1 1
MSB OTR LSB
MSB 0 1 0 1
Analog Input Is In Range In Range Underrange Overrange
OVER = "1"
UNDER = "1"
70
CLOCK INPUT
S/(N+D) - dB
Figure 21. Overrange or Underrange Logic
65
The AD1672 internal timing control uses the two edges of the clock input to generate a variety of internal timing signals. The clock input must meet or exceed the minimum specified pulse width high and low (tCH and tCL) specifications of 167 ns to maintain the AD1672's rated performance. At a clock rate of 3 MSPS, the clock input must have a 50% duty cycle to meet this timing requirement. For clock rates below 3 MSPS, the duty cycle may deviate from 50% to the extent that both tch and tcl are satisfied. One way to minimize the tolerance of a 50% duty cycle clock is to divide down a clock of higher frequency, as shown in Figure 22.
60
55
50 0 0.5 1 1.5 2 2.5 3 3.5 FREQUENCY - MHz 4 4.5 5
Figure 23. Typical S/(N+D) vs. Clock Frequency; fIN = 500 kHz, Full-Scale Input
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AD1672
The power dissipated by the correction logic and output buffers is largely proportional to the clock frequency; running at reduced clock rates provides a slight reduction in power consumption. Figure 24 illustrates this tradeoff.
260
75 DRVDD 70 65 VDD
S/(N+D) - dB
60 55 50
258 256
VCC
POWER - mW
254 252 250 248 246 244 0 0.5 1 1.5 2 2.5 3 3.5 FREQUENCY - MHz 4 4.5 5
45 40 0.1
0.2
2 0.5 1 FREQUENCY - MHz
5
10
Figure 26. S/(N+D) vs. Supply Noise Frequency
Figure 24. Typical Power Dissipation vs. Clock Frequency
GROUNDING AND POWER SUPPLY DECOUPLING RULES
power supply ripple at various frequencies. Figure 26 shows the degradation in S/(N+D) ratio resulting from this 100 mV power supply ripple for a full-scale analog input at 500 kHz. The AD1672/EB evaluation board was used to generate these graphs The AD1672 is designed to minimize the code dependent current at REFCOM, therefore reducing input dependent analog ground voltage drops and errors. The majority of code dependent ground current is diverted to ACOM. The digital activity on the AD1672 chip falls into two general categories: CMOS correction logic, and CMOS output drivers. The internal correction logic draws relatively small surges of current which flow through VDD and DCOM. The output drivers draw large current impulses while the output bits are changing. The size and duration of these currents is a function of the load on the output bits: large capacitive loads are to be avoided. The output drivers are supplied through DRVDD and DRCOM. A 0.1 F ceramic capacitor for decoupling the driver supply, DRVDD, is appropriate for a reasonable capacitive load on the digital outputs (typically 20 pF on each pin). Applications involving greater digital loads should consider increasing the digital decoupling proportionately. For those applications that require a single +5 V supply for both the analog and digital supply, a clean analog supply may be generated using the circuit shown in Figure 27. The circuit consists of a differential LC filter with separate power supply and return lines. Lower noise can be attained using low ESR (Equivalent Series Resistance) type electrolytic and tantalum capacitors.
TTL/CMOS LOGIC CIRCUITS FERRITE BEADS +5V 100F ELECT. 10-20F TANT. 0.1F CER. AGND +5V DGND
Proper grounding and decoupling should be a primary design objective in any high speed, high resolution system. The AD1672 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. In general, VCC, the analog supply, should be decoupled to ACOM, the analog common, as close to the chip as physically possible. Similarly, VDD, the digital supply, should be decoupled to DCOM as close to the chip as physically as possible. DRVDD, the digital supply for the output drivers should be decoupled to DRCOM which is also connected to the digital ground plane. Figure 31, the AD1672/EB evaluation board schematic, demonstrates the recommended decoupling strategy for the supply pins. Note that in extremely noisy environments, a more elaborate supply filtering scheme may be necessary. Figure 25 shows the power supply rejection ratio vs. frequency for 100 mV of
-30 -40 -50
SUPPLY REJECTION - dB
VCC -60 -70 -80 -90 DRVDD VDD
-100 -110
-120 0.1
0.2
0.5 1 2 FREQUENCY - MHz
5
10
+5V POWER SUPPLY
Figure 25. Power Supply Rejection vs. Frequency, 100 mV p-p Signal on Power Supplies
Figure 27. Differential LC Filter for Single +5 V Applications
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AD1672
GAIN AND OFFSET ADJUSTMENT
The AD1672 is factory trimmed to minimize gain, offset and linearity errors. In some applications, the gain and offset errors need to be externally trimmed to zero. Since the gain and offset errors of the AD1672 are interdependent, an iterative process is required to trim both errors. The OTR pin can be monitored to trim the offset and gain errors to within 1/2 LSB of negative and positive full-scale (i.e., -FS and +FS) respectively. In this case, the calibration procedure would be to iterate between -FS and +FS voltage levels which are applied to the input of the AD1672 and adjust the offset and gain until OTR toggles at both -FS and +FS. Both gain and offset errors may be trimmed with external calibration circuits based on a potentiometer or a DAC. Digital calibration circuits using a DAC offers greater flexibility and can be programmed for various operating conditions. The following digital calibration circuits are based on the DAC08 which is a low cost, 8-bit current output DAC with 85 ns settling time performance. Different adjustment spans and resolution may be achieved by judicious selection of the resistors in the circuit. Figure 28 shows an offset correction circuit for the unipolar input ranges of 0 V to 2.5 V and 0 V to 5.0 V. The complementary current outputs of the DAC08 provide a bipolar adjustment range at the output of the op amp if RS is made equal to RF/G. G is the noninverting gain of the op amp and is equal to 1 + RF/RA. REFOUT divided by RIN sets the full-scale current output, IFS, for the DAC08 Note, RP is a pull-up resistor used to source additional current if IFS is greater than 500 A. The bipolar voltage adjustment span at the output of the op amp is equal to IFS x RF. RI isolates the op amp from the DAC08 output capacitance. Note, that the values of these resistors can be optimized for any circuit requirement or adjustment span since they are not uniquely defined for any given voltage span.
RS
RF
AIN RA +VCC RP REFOUT
RI
RI
AD1672
RIN IO IO VREF(+)
DAC08
VREF(-)
RIN
1F
Figure 29. Bipolar Offset Correction Using the DAC08
Figure 30 shows a gain correction circuit which is also similar to the circuit shown in Figure 28. The circuit consists of a unity gain amplifier in which RS and RF are equal to 158 . In this case, the full-scale output current of the DAC08, IFS, is set at 500 A to minimize the load to the AD1672 REFOUT. The output of the op amp can be varied over a 78 mV range around the midscale voltage of REFOUT. Also, RS and RF are selected such that 1 LSB of the DAC08 corresponds to 1 LSB of the AD1672.
2.5 0.078V +VCC 4.7k 500 5k IO 500 IO VREF(+) REFOUT 2.5V 1F
REFIN
158
AD1672
DAC08
VREF(-) 158
5k
Figure 30. Gain Correction Using the DAC08
OUTPUT LATCHES
AIN RF RA +VCC RP REFOUT RIN 1F
RI
RI
AD1672
RIN IO IO VREF(+)
The AD1672/EB evaluation board schematic in Figure 31 shows the AD1672 connected to the 74HC541 octal/buffer line drivers with three-state outputs. The latch can drive highly capacitive loads (i.e., bus lines, I/O ports) while maintaining the data signal integrity.
AD1672 EVALUATION BOARD GENERAL DESCRIPTION The AD1672/EB is an evaluation board for the AD1672 12-bit 3 MSPS analog-to-digital converter (ADC). Figure 31 shows the schematic for the AD1672/EB evaluation board. Careful attention to layout and circuit design combined with analog and digital prototyping areas allows the user to easily and effectively evaluate the AD1672 in any application requiring high resolution, high speed conversion.
DAC08
VREF(-)
Figure 28. Unipolar Offset Correction Using the DAC08
Figure 29 shows an offset correction circuit for the bipolar input range of -2.5 to +2.5 V. This circuit is similar to the circuit shown in Figure 28 except that the op amp is configured in an inverting topology so that the voltage compliance of the DAC08 is not exceeded.
The analog input to the AD1672/EB may be driven directly or via an onboard buffer amplifier. The AD1672/EB contains an 8-bit DAC which can be easily configured for input offset adjustment or for reconstruction of the digital output. An optional external voltage reference is included for greater dc precision
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AD1672
and/or offset adjustment purposes. Onboard data buffers are also included. The AD1672/EB requires an external clock which is applied from a user's bench or generated from a circuit built on the prototyping area. A standard 40-pin IDC-connector provides access for the digital outputs from the AD1672/EB. The user must also provide a digital +5 V power supply and analog 5 V supplies to operate the AD1672/EB.
OPERATING PROCEDURE AND FUNCTIONAL DESCRIPTION Power
The AD1672's analog input range can be configured for 0 V-2.5 V, 0 V-5 V, or 2.5 V by installing only one of the four jumpers, JP5-JP7, as outline in Table VII. JP5 JP6 JP7 Installing only jumper JP5, the 0 V-2.5 V range of the AD1672 is selected. Installing only jumper JP6, the 0 V-5 V range of the AD1672 is selected. Installing only jumper JP7, the 2.5 V range of the AD1672 is selected.
Table VII. Analog Input Range Selection
Apply power to the AD1672/EB by attaching banana plugs to the appropriate banana jacks on the printed circuit board (Figure 31). The +VCC analog supply should be +5 V ( 5%) and be capable of supplying 70 mA. The -VEE analog supply should be -5 V ( 5%) and be capable of supplying 20 mA. The +VDD digital supply should be +5 V ( 5%) and be capable of supplying 12 mA (not including any additional current required by the digital load). The power supply pin for the onboard output drivers internal to the AD1672 (DRVDD-Pin 14) can be driven directly by the digital supply, +VDD, by installing JP10 or may be driven via a separate supply by removing JP10 and driving the test point, TP5. The separate supply option allows the user to interface with +5 V or +3.3 V ( 5%) logic families. JP1 To provide +VCC supply to both U3 (DAC08) and U1 (op amp), attach jumper JP1.
Analog Input Range (Volts) 0 to 2.5 0 to 5.0 2.5
Reference
JP5 ON OFF OFF
JP6 OFF ON OFF
JP7 OFF OFF ON
An external 2.5 V voltage reference, U2, is also included on the AD1672/EB to provide the option for greater dc precision than the AD1672's internal reference. The external reference also provides the proper biasing currents for the offset adjustment circuitry consisting of U3. To use the external voltage reference for the AD1672, install JP9 and remove JP4. To use the AD1672's internal voltage reference, install JP4 and remove JP9. JP4 JP9 Installing JP4 and removing JP9 selects the AD1672's internal reference. Installing JP9 and removing JP4 selects the external reference, U2.
JP10 To provide +5 V (+/-5%) supply to DRVDD pin of AD1672 via +VDD or separate supply. To provide power to DRVDD pin via +VDD, install JP10. To provide power to DRVDD pin via separate supply, remove JP10 and connect external supply to test point TP5.
Analog Inputs
Offset Adjustment/Reconstruction DAC
The BNC jack, AIN (J1), accepts voltage inputs that comply with the analog input requirements of the AD1672. It is terminated with a 49.9 resistor (R1) located on the componentside of the evaluation board. Remove and/or replace this resistor with other values in order to match different cable impedances. The AD1672 analog input can be directly driven via AIN (J1) by installing JP2 and removing JP3 or it can be driven via an amplifier (U1) by installing JP3 and removing JP2. The amplifier (U1) may be configured in the inverting or noninverting mode with a gain of one by configuring S4. JP2 JP3 Installing JP2 and removing JP3, directly dc couples AIN (J1) to the AD1672 analog input. Installing JP3 and removing JP2, indirectly dc couples AIN (J1) to the AD1672 analog input via the inverting op amp U1. Selects inverting or noninverting gain of one for the amplifier U1. When S4 is in position A, the noninverting mode is selected. When S1 is in position B, the inverting mode is selected.
An 8-bit complementary current output DAC08, U3, allows for either offset adjustment of the analog input or reconstruction of the AD1672 digital output for simple evaluation purposes. The offset adjustment option is implemented by installing both JP3 and JP8. Note that JP5, JP6 and JP7 should be removed so that the AD1672 is configured for a 0 V-5 V range. The DAC08 can also be configured to reconstruct the digital output of the AD1672 using its digital output for the DAC08's digital input. The output of the user supplied ribbon cable used to interface with the 40-pin IDC connector (E1) can be connected directly to the connector U8, hence recirculating the eight most significant digital output bits of the AD1672. In this configuration, JP8 would be removed and the reconstructed waveform ( 50 mV p-p) can be monitored via test point TP4. JP8 Installing JP8 and removing JP5, JP6 and JP7 selects the offset adjustment option. Removing JP8 and connecting E1 to U8 via an external user-supplied ribbon cable selects the reconstruction option.
S4
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AD1672
Clock Input
A 49.9 resistor (R9) terminates this input. Remove and/or replace this resistor with other values in order to match different cable impedances. An external sample clock must be provided to the BNC connector labeled CLK (J5). The rising or falling edge of CLK can be selected to trigger a conversion and is available to the user via the connector E1 by configuring S1 and S3. The CLK INPUT has two modes of operation which is determined by the position of S5. When S5 is in Position B, the CLK is directly coupled to U5, a Hex inverter with Schmitt trigger inputs. The requisite input levels are CMOS-compatible in this mode. When S5 is in Position A, the CLK is ac coupled via C23 and level shifted via R10, R12, and R13. This mode is used to generate a low jitter clock input for the AD1672 with a tunable duty cycle. The input to CLK (J5) is a filtered 5 V p-p sine wave at the desired sampling frequency. The duty cycle may be adjusted via R10. S1 Selects the rising or falling edge of CLK to initiate a conversion. When S1 is in Position A, the falling edge of CLK is selected. When S1 is in Position B, the rising edge of CLK is selected. Selects the rising or falling edge of CLK made available to the user via the connector via E1, Pin 33. When S3 is in Position A, the rising edge of CLK is selected. When S1 is in Position B, the falling edge of CLK is selected. Selects CLK INPUT mode of operation. If S5 is in Position A, the low jitter, ac coupled mode of operation is selected. If S5 is Position B, the dc coupled mode of operation is selected.
A summary of the test point designators and a parts list is given in Table VIII and IX.
Table VIII. Summary of Test Point Designators
Test Point TP1 TP2 TP3 TP4 TP5 TP6
TP7
Description AGND AIN VCC for U1 and U3 DAC08 (U3) VOUT DRVDD DGND
CLK
Table IX. AD1672 EB Parts List
Reference U1 U2 U3 U4 U5 U6, U7 AIN, CLK JP1-10 S1-S5 E1 R1, R9 R2-R4 R11-R13 R5 R6 R7, R8 R10 C1, C2, C4, C12-C16, C18-C20 C3, C6-C9, C11, C22, C23 C5, C17, C21 C10 C24
Value/Part Type AD8047 REF192 DAC08 AD1672 74HC14N 74HC541N BNC JACKs Headers/Shunts SPDT, Secme 40-Pin IDC Connector 50 499 4.99 k 100 2.49 k 2.0 k POT 0.1 F 1.0 F 10 F 0.01 F 47 F
Package 8-Pin DIP 8-Pin DIP 16-Pin DIP 28-Pin PLCC 14-Pin DIP 20-Pin DIP Small, Vertical 2-Pin 0.1" x 0.3" R.A., Male w/Latches 1%, 1/4 1%, 1/4 1%, 1/4 1%, 1/4 1%, 1/4 1%, 1/4 Ceramic, SMT
Qty/Bd 1 1 1 1 1 2 2 10 5 1 2 6 1 1 2 2 11
S3
S5
Digital Inputs/Outputs
The digital outputs of the AD1672 are buffered and connected to a 40-pin IDC connector (E1). The digital output can be either in a straight binary or twos complement format by configuring S2. S2 selects the MSB output or its complement. The Out-of-Range (OTR) output is available on test point, OTR. S2 Selects either the MSB or its complement for either straight binary or twos complement digital output data formatting, respectively. When S2 is in Position A, the straight binary format is selected. When S2 is in Position B, the twos complement format is selected.
Layout Considerations
Figure 31 to 34 show the schematic diagram, component layout, trace routing, and silk screening for the AD1672 4-layer evaluation board. Figure 35 and 36 show the AD1672 ground and power plane layouts. The AD1672-EB is a 4-layer evaluation board consisting of separate ground and power plane layouts. Separate ground and power planes have several advantages for high speed layouts. (For further information outlining these advantages, see the application note "Design and Layout of a Video Graphics System for Reduced EMI" [E1309] available from Analog Devices [(617) 461-3392].) The ground planes are separated into analog and digital planes that are joined together under the AD1672. The AD1672 should be treated as an analog component and a common ground connection should be made underneath the AD1672 despite some pins being labeled "digital" and some as "analog" ground plane.
Ceramic, Throughhole Tantanlum Throughhole Ceramic Alum. Elect.
8 3 1 1
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R7 2.5k TP4 EREF JP10 OTR C22 1F 1 3 5 7 9 +VDD +VCC E1 E1 2 E1 E1 E1 11 E1 13 E1 4 6 8 10 12 14 16 15 E1 17 E1 19 E1 21 E1 23 E1 25 E1 +VDD 27 E1 4 3 C20 0.1F 29 E1 18 20 22 24 E1 E1 E1 E1 E1 E1 E1 E1 E1 E1 E1 E1 26 E1 28 E1 30 E1 32 34 36 E1 E1 E1 +VDD TP5 C13 0.1F
R8 2.5k
14 VREF(+)
VREF(-)
15
74HC541N
U3
A
IO- -VEE R6 100
A
4
R5 5k
VEE
3
U8 U8 U8 U8 U8 U8 U8 U8
2 4 6 8 10 12 14 16
U8 1 U8 3 U8 5 U8 7 U8 9 U8 11 U8 13 U8 15
5 6 7 8 9 10 11 12
A1 A2 A3 A4 A5 A6 A7 A8
NC 2 VIN VOUT GND C16 0.1F JP9 11 23 9 JP4
A A A A
1
REF192 U2
6 C8 1F 13 26 12 15 14
A
C15 0.1F C4 0.1F 4
A
A DAC08 13 VCC COMP 16 2 GND C10 A 0.1F +VCC TP3 C1 0.1F 20 8 C6 1F 10
1 G1 19 G2 2 Y0 A0 3 Y1 A1 4 A2 U6 Y2 5 Y3 A3 6 Y4 A4 7 Y5 A5 8 Y6 A6 9 Y7 A7 10 GND +5VD 18 17 16 15 14 13 12 11 20 C19 0.1F
JP1
74HC541N
TP2
6 A
J1 21 JP3 JP5 22 JP7 JP8 24 3 18 2 1
A
3
AIN 7 6 5 4 R3 500
S4 A
7
AD8047
U4
R4 500
U1
AD1672
2
4
R1 50
B
A
TP1 JP6
A
R2 C2 500 0.1F
JP2
A
-VEE
-17-
U5
+VDD 17 C12 0.1F 19 C11 1F
1 G1 19 G2 2 Y0 A0 3 Y1 A1 4 A2 U7 Y2 5 Y3 A3 6 Y4 A4 7 Y5 A5 8 Y6 A6 9 Y7 A7 10 GND +5VD
18 17 16 15 14 13 12 11 20
J3
TP9
AGND
AGND
S2
A B
74HC14
38 31 E1 33 E1 40
E1 E1
A
J7
A
TP12 27 +VCC 28 C14 0.1F 25
A A
+VDD C9 1F C7 1F
+VDD
S3
R11 500 +VDD
A
35 E1 B 37 E1
J6
TP11
C21 10F 16V
DGND 16 TP7 J5 CLK R9 50
DGND
TP10
9 A R12 500 C23 1F C24 47F CW
U5 S5
B R10 2k 1 R13 500 A 5
39 E1 8
J4
U5
+VCC
+VCC
6
74HC14 74HC14 U5
11
J2
TP8
C17 10F 16V
U5
+VDD 10
A
-VEE
-VEE
74HC14
2 13
C18 0.1F
C5 10F 16V TP6
C1 1F
U5 74HC14 S1
12
A
74HC14
AD1672
B
Figure 31. Evaluation Board Schematic
AD1672
Figure 32. PCB Component Side Layout for Evaluation Board
Figure 33. PCB Solder Side Layout for Evaluation Board
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AD1672
Figure 34. PCB Component Side Silkscreen
Figure 35. PCB Ground Plane Layout for AD1672
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Figure 36. PCB Power Plane Layout for AD1672
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
28-Lead PLCC (P-28A)
0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07)
26 25
0.048 (1.21) 0.042 (1.07) 0.048 (1.21) 0.042 (1.07)
0.025 (0.63) 0.015 (0.38) 0.021 (0.53) 0.013 (0.33)
4 5 PIN 1 IDENTIFIER
TOP VIEW
(PINS DOWN) 11 12 19 18
0.050 (1.27) BSC
0.032 (0.81) 0.026 (0.66)
0.430 (10.92) 0.390 (9.91)
0.020 (0.50) R
0.456 (11.58) SQ 0.450 (11.43) 0.495 (12.57) SQ 0.485 (12.32)
0.040 (1.01) 0.025 (0.64) 0.110 (2.79) 0.085 (2.16)
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PRINTED IN U.S.A.
C2049-10-7/95

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